Important note: Data sourced from the 2024 Wilson Research Group IC/ASIC Functional Verification Trend Report by Siemens EDA. Original report available here. As I am an ASIC/IC Verification Engineer, I haven’t taken the report about FPGAs into account in this article, but It’s a good read, too.
Why This Report Matters to Me
I came across the 2024 Wilson Research Group study during my recent job search, while exploring where I should focus my professional development. As someone looking to advance in the semiconductor industry, this report proved to be the most relevant and up-to-date resource for understanding current verification challenges and opportunities. The findings have helped shape my perspective on which skills will be most valuable in the coming years and where the greatest industry needs exist. What began as personal notes in a Word document—reminding me of how I used to summarize research during my university years—has evolved into insights I believe are worth sharing with the broader community.
Key Findings: A Troubling Picture
For me, the most noticeable (and concerning) takeaway of this year’s report is that only 14% of IC/ASIC projects achieved first-silicon success in 2024, the lowest level recorded in two decades. This decline comes despite substantial increases in verification effort and resources, suggesting a fundamental disconnect between growing design complexity and our ability to verify these designs effectively.
The study reveals several factors driving this complexity:
- Embedded processor: 84% of projects now incorporate one or more embedded processors, with RISC-V adoption nearly doubling to 58%
- AI integration: 59% of projects include AI accelerator processors, almost twice the previous study’s figure
- Multiple clock domains: 95% of designs contain two or more asynchronous clock domains
- Security requirements: 83% of projects implement security features
- Safety-critical standards: 44% of projects adhere to one or more safety-critical standards
Looking complex, right? This complexity is putting pressure on project timelines, with 75% of IC/ASIC projects behind schedule in 2024, up from 66% historically.
Verification Demands Growing
The verification burden continues to increase, with design engineers spending nearly half (49%) of their time on verification activities rather than design. Verification engineers spend most of their time (21%) debugging – an unpredictable activity that complicates project planning.
In some market segments, particularly processors, the verification-to-design engineer ratio has reached 5-to-1. This reflects how validation has become the dominant cost center in modern chip development.
Methodological Adaptation
The industry isn’t standing still. The study shows growing adoption of advanced verification methodologies:
- SystemVerilog and UVM dominate for testbenches
- Formal verification techniques are gaining traction (5.8% CAGR for property checking)
- Code coverage (70%), functional coverage, assertions, and constrained-random simulation see high adoption
- Emulation and FPGA prototyping usage is rising, especially for designs exceeding 1 billion gates
Methodological Concerns
While the Wilson study provides valuable insights, we should approach its findings with appropriate skepticism. General Things I kept reminding myself while reading the report:
- Causal analysis gaps: While the report identifies correlations (like declining first-silicon success rates), it doesn’t thoroughly explore whether this stems from increasing complexity, workforce issues, or other factors. I think this is the biggest gap in this great report.
- Insufficient temporal resolution: The data points in the report (2012, 2016, 2020, 2024) are spaced 4 years apart, which is an extremely long interval in the fast-moving semiconductor industry. This wide spacing makes it difficult to identify short-term trends, inflection points, or correlate changes with specific industry events (economic cycles, COVID…).
- Regional sampling bias: The study acknowledges a 15% decline in East Asian participation with increased North American representation, potentially skewing technology adoption trends.
- Industry connections: Though steps were taken to prevent vendor bias, the study was commissioned by Siemens EDA, which sells verification tools – creating potential conflicts of interest.
The Verification Challenge Ahead
Despite these methodological limitations, I think the overall trend is clear: verification challenges are outpacing our ability to solve them with current approaches. As designs incorporate more embedded processors, security features, and safety-critical requirements, the industry faces a critical point.
The report highlights debugging as the primary bottleneck in verification, with “logic or functional flaws” remaining the leading cause of bugs. Simultaneously, the talent gap in verification engineering continues to widen just as demand grows.
Looking Forward
For the semiconductor industry to continue advancing, several priorities emerge:
- Connected, data-driven verification solutions that can scale with increasing design complexity
- Workforce development initiatives to address the verification engineer shortage or lack-of-expertise (better temporal resolution could have told us what could be the real problem).
- More sophisticated debugging tools to address the largest time sink in verification.
The 2024 Wilson Research Group Study presents both warning signs and opportunities. While first-silicon success rates have reached concerning lows, the industry continues to adapt with new methodologies and tools. The question remains whether these adaptations can keep pace with (probably) exponentially growing design complexity.
back to me…
As mentioned at the beginning of this post, I encountered this report while researching career development opportunities in the semiconductor industry. The findings have significant implications for professionals like myself:
- Verification expertise is increasingly valuable: With verification engineers in high demand (reaching a 5-to-1 ratio with design engineers in some sectors), specializing in verification methodologies offers strong job security and growth potential.
- Critical skill areas: The report highlights several high-value skill areas worth developing:
- Debugging techniques (addressing the biggest verification bottleneck)
- Formal verification methods (showing consistent growth in adoption)
- Safety and security verification (as these requirements become standard)
- Emulation and FPGA prototyping expertise (especially for complex designs)
- Interdisciplinary knowledge: The increasing overlap between hardware and software verification suggests that professionals who understand both domains will be particularly well-positioned.
For me, this report doesn’t just represent industry statistics—it’s a roadmap for professional development in a rapidly evolving field. I’m sharing these insights in hopes that others might also find direction in their own career journeys within this challenging but exciting industry.
