Explore my collection of projects, technical insights, and creative endeavors. As a Verification Engineer with a passion for electronics, coding, and innovation, I document my journey through various fields of interest - from advanced SoC verification techniques to weekend DIY electronics projects and everything in between.
Here you'll find detailed write-ups of my professional challenges, hobby projects, and occasional thoughts on technology trends. Whether you're a fellow engineer looking for technical insights or just curious about what happens when engineering minds explore beyond their day jobs, there's something here for you.
Dive in and discover the intersection of professional expertise and passionate curiosity!
Discover how AI is transforming hardware verification in 2025, as discussed by Abhi Kolpekwar (VP at Siemens) on "The DV Digest" podcast. Explore the evolving role of verification engineers, the impact of artificial intelligence on EDA tools, and the real-world shift from hype to practical results in chip design and testing.
Stanford study reveals AI is already displacing young developers while older engineers thrive. As a verification engineer using AI tools daily, here's what this means for hardware careers.
Every verification engineer I’ve talked with since this AI thing started has told me the same thing: “It’s far from excellent.” And honestly, it looked like if you don’t write fullstack JavaScript or Python, ChatGPT or Claude’s code generation will…
I’ve been there more times than I’d like to admit. I start a new project with fire in my belly – every small win feels electric, every line of code or sketch on paper brings me closer to something amazing.…
Learn how to set up remote debugging for CocoTB and PyUVM hardware verification tests using VSCode and debugpy. This step-by-step guide shows you how to inspect variables, set breakpoints, and step through PyUVM code execution while running tests on a remote machine.
While traditional UVM uses SystemVerilog's concurrent constructs (fork-join, always, etc.), Python's async/await syntax provides a cleaner and more explicit approach to concurrency. This is particularly valuable in hardware verification, where we constantly need to model parallel processes, handle timing, and manage complex interactions between components.
In Part 1, we explored the fundamental components of pyUVM and how they compare to traditional SystemVerilog UVM. We covered transactions, drivers, monitors, coverage, and scoreboards – the building blocks of any verification environment. In Part 2, we’ll dive deeper…
Part 1 of my 2-part guide on transitioning from SystemVerilog UVM to pyUVM. Compare verification components like transactions, drivers, and scoreboards with real TinyALU examples. Learn how Python features simplify verification workflows for modern engineers. Continue to Part 2 for advanced features.
This is the first in a series of tutorials exploring Python-based hardware verification. As someone with experience in SystemVerilog UVM, I’m investigating whether Python-based verification frameworks like Cocotb and PyUVM offer advantages over traditional approaches. Join me on this journey as I learn, experiment, and share my findings. In this post, we’ll set up Cocotb and run our first testbench. In the next post, we’ll explore PyUVM.
Introduction Throughout my verification career, I’ve consistently used uvm_config_db as my go-to mechanism for sharing data between components in UVM testbenches. It’s ubiquitous in training materials, example code, and verification environments. However, after reading Cliff Cummings’ illuminating paper “The Untapped…